1. Field of the Invention
The present invention relates to the field of programmable circuits and, in particular, to programmable logic devices.
2. Description of Related Arts
FIG. 1 shows a typical programmable circuit 30 such as a programmable logic device which contains an array of logic gates that can be connected or programmed to perform various functions. Programmable circuit 30 includes a product term array 10, a plurality of sense amplifiers 1 through m, product term matrix (PTM) blocks/OR gates 40-1 through 40-k, configuration bits blocks 42-1 through 42-k, macrocell blocks 44-1 through 44-k, and output drivers 46-1 through 46-k. Product term array 10 and sense amplifiers 1 through m form a programmable AND plane, and PTM blocks/OR gates 40-1 through 40-k and configuration bits blocks 42-1 through 42-k form a programmable OR plane.
Product term array 10 is used to implement programmable AND functions. Product term array 10 includes rows of programmable cells where each of the cells can be either erased or programmed. Each of the programmable cells receives a true input (such as input 11 or input m1) or a bar input (such as input 11, input 1n, input m1, or input mn). A bar input is usually an inverted signal of its true input. Because input 11 is a true input while input 11 is a bar input, if input 11 receives a logic 1, then input 11 receives a logic 0. Product term array 10 can be programmed according to desired AND equations by providing appropriate logic values to its inputs, and by programming or not programming each of the cells appropriately.
Each of sense amplifiers 1 through m is used to detect the logic states of its corresponding row of the programmable cells in product term array 10. In a given row, if any of the programmable cells conducts, then its corresponding sense amplifier's output is typically low for a noninverting sense amp and high for an inverting sense amp. If, on the other hand, none of the programming cells in a given row conducts, then its corresponding sense amplifier's output is high for noninverting sense amp. A detailed circuit schematic representation of the programmable cells and a sense amplifier will be shown later in FIG. 2.
PTM blocks/OR gates 40-1 through 40-k are used to implement 0R functions. Each of the sense amps 1 through m can be connected to one or more PTM blocks/OR gates 40-1 through 40-k.
Configuration bits blocks 42-1 through 42-k are used to configure their corresponding PTM blocks/OR gates. For instance, if sense amplifiers 1, 3, 5, and 7 are connected to PTM block/OR gate 40-1, then configuration bits block 42-1 provides a configuration bit for each of sense amplifiers 1, 3, 5, and 7. The outputs of sense amplifiers 1, 3, 5, and 7 are either used or not used in the PTM block/OR gate 40-1 depending on the states of their corresponding configuration bits provided by configuration bits block 42-1. The operation of PTM blocks/OR gates and configuration bits blocks will be described more in detail later with respect to FIG. 3.
Each of macrocell blocks 44-1 through 44-k can be implemented as a latch, D register, or T register. Each of output drivers 46-1 through 46-k is used to drive an output from its corresponding macrocell block.
FIG. 2 is a combination of a block diagram and a circuit schematic representation of a first row of product term array 10 and sense amplifier 1 in FIG. 1. A programmable cell may be implemented in various way. An example of a programmable cell, such as cell 11a, typically includes (a) a transistor for receiving an input and (b) a nonvolatile cell. Cell 11a includes an NMOS transistor M10 for receiving input 11 and a nonvolatile cell 11 which includes two floating gate devices M12 and M14. Floating gate device M12 can be either erased (e.g., the floating gate of the non-volatile cell is not programmed or the nonvolatile cell is capable of conducting) or programmed. Floating gate device M14 is used to erase floating gate device M12. Similarly, cell 11b is constructed in the same manner as cell 11 (etc.).
In operation, if floating gate device M12 is erased and input 11 is high, then both transistors M10 and M12 conduct. If a reference voltage Vref 1 is applied, then a current limiting device M28 conducts, and A11 is pulled down low. When any one of the cells is erased and its corresponding M10, a pass gate, is on, line A11 is low regardless of the states of other programmable cells. Thus, when cell 11a is on (conducting), line A11 is low. Line A11 is in a high state only if all of the programmable cells in the row are programmed, or for the unprogrammed cells, the corresponding M10 devices are off, (i.e., not conducting ). Thus SAout in FIG. 3 acts as an output of the programmable AND plane while the inputs to the programmable cells act as inputs to the programmable AND plane.
As described above, the entire cell 11a is on (conducting), if floating gate transistor M12 is erased, and input 11 is high. If, on the other hand, input 11 is low, and the pass gate M10 is off, line A11 is high regardless of whether the nonvolatile transistor ME12 is erased or programmed. Also, line A11 is high, if nonvolatile transistor M12 is programmed regardless of whether input 11 is high or low.
Continuing to refer to FIG. 2, sense amplifier 1 includes., in one embodiment, three gain stages (a stage 1, a stage 2, and a stage 3) and current limiting device M28. Sense amplifier 1 includes three gain stages so that full rail logic levels can be achieved at a sense amplifier output node (SAout) 1. It will be appreciated that other embodiments of sense amps may be used.
In operation, if line A11 is low, then a node 1 in sense amplifier 1 is high, turning on a transistor M26 so that SAout 1 is low. If, on the other hand, line A11 is high, then node 1 is low, turning off transistor M26. When a reference voltage Vref 2 is applied, a transistor M24 conducts, and thus SAout 1 is high. While the logic levels at line A11 do not reach the full rail logic levels, the logic levels at SAout 1 reach the full rail logic levels.
Current limiting device M28 is provided to limit the current that can be drawn from product term array 10.
FIG. 3 is a combination of a block diagram and a circuit schematic representation of PTM block/OR gate 40-1. It will be appreciated that FIG. 3 shows one embodiment of the PTM blocks and other embodiments may be used. PTM block/OR gate 40-1 can be connected to any number of the sense amplifiers in FIG. 1. For illustration purposes only, in FIG. 3, PTM block/OR gate 40-1 is connected to sense amplifiers 1, 2, and m. The output signals of the sense amplifiers 1, 2, and m are shown as SAout 1, SAout 2, and SAout m, respectively. SAout 1 is an input for a transistor M44, SAout 2 is an input for a transistor M46, and SAout m is an input for a transistor M48.
For each of the sense amplifiers that is connected to PTM block/OR gate 40-1, configuration bits block 42-1 in FIG. 2 provides a configuration bit. Configuration bits cf1, cf2, and cfm are provided for sense amplifiers 1, 2, and m, respectively. If SAout 1 is to be used in PTM block/OR gate 40-1, then cf1 is high. Similarly, if SAout 2 or SAout m is to be used in PTM block/OR gate 40-1, then cf2 or cfm, respectively, is high.
Typically, a configuration bit is high if the configuration cell that produces the configuration bit is programmed, and a configuration bit is low if the configuration cell of the configuration bit is erased. The structure of a configuration cell is similar to the structure of a programmable cell such as cell 11a shown in FIG. 2.
In FIG. 3, if a configuration bit is high, then its corresponding sense amplifier output can affect the value at line C, that is, the sense amplifier output is used in PTM block/OR gate 40-1. However, if a configuration bit is low, then its corresponding sense amplifier output does not affect the output at line C, that is, the sense amplifier output is blocked from being used in PTM block/OR gate 40-1. For instance, if cf1 is high, then line C can be affected by SAout 1. In that instance, if SAout 1 is high, then line C is low. If, on the other hand, cf1 is low, then transistor M54 is off, and line C is not affected by SAout 1.
An OR sense amplifier (ORSAmp) 60 is a sense amplifier which may be similar in structure to sense amplifier 1 shown in FIG. 2. Thus, the detailed circuit schematic representation of ORSAmp 60 is omitted. ORSAmp 60 detects the logic level at line C and provides the full rail logic level at its output node ORSAout 63.
Since sense amplifiers such as sense amplifiers 1 through m consume a large amount of power when they are not used, it is beneficial to disable any unused sense amplifiers. Conventionally, there are three ways of disabling unused sense amplifiers. First, a sense amplifier can be disabled in a high current state (for the current embodiment) if all of the programmable cells connected to the sense amplifier are erased. For example, in FIG. 2, if all of programmable cells 11a, 11b, . . . , cell 1nb are erased, then since half of the cells are connected to true inputs while the other half of the cells are connected to bar inputs, some of the cells must conduct, and thus line A11 becomes low. Hence, SAout 1 is pulled low regardless of the input values. In this instance, sense amplifier 1 is disabled (for the current embodiment) in a high current state because a large current flows from some of the programmable cells through M28, and all of the stages conduct current.
Second, a sense amplifier can be disabled in a low current state (for the current embodiment) if all of the programmable cells connected to the sense amplifier are programmed. For instance, in FIG. 2, if all of the programmable cells (cell 11a, cell 11b, . . . , cell 1nb) are programmed, then regardless of the input values, line A11 is high. Hence, SAout 1 is pulled up high. In this instance, sense amplifier 1 is disabled (for this embodiment) in a low current state and only stage 2 burns significant current.
Third, a sense amplifier can be disabled by including additional circuitries, as shown in FIG. 4. A programmable circuit 30' shown in FIG. 4 is the same as programmable circuit 30 in FIG. 1 except that programmable circuit 30' includes disabling configuration bit blocks 41'-1 through 41'-m used to disable sense amplifiers 1' through m'. Disabling configuration bit blocks include configuration bit cells, configuration bit sense amplifiers, and other programming circuits.
Conventional schemes of disabling unused sense amplifiers have several drawbacks. Although the first scheme described above does not require any additional circuitry to disable an unused sense amplifier, that scheme is disadvantageous because it consumes a large amount of current.
The second scheme can be more advantageous than the first scheme because the disabled sense amplifiers consume less current than those sense amplifiers disabled according to the first scheme. However, the second scheme requires programming of the programmable cells in the product term array. Also, although the disabled sense amplifiers are in a low current state, the sense amplifiers still consume a large amount of current. In addition, because of the significant power consumed by the disabled sense amplifiers, the operating temperature of the circuit increases, and hence, the circuit performance degrades.
The third scheme may be more advantageous over the first two schemes described since the sense amplifiers disabled by the third scheme consume only a minimum or no power. However, the third scheme requires an additional disabling configuration bit circuitry for each sense amplifier where the disabling configuration bit circuitries include configuration bit cells similar to programmable cells of product term array 10' in FIG. 4, configuration bit sense amplifiers, and other programming circuits such as input term decoders, product term decoders, etc. Hence, disabling configuration bit circuitries can become complex.
Therefore, it is desirable to be able to disable sense amplifiers at a minimum current level while requiring the least amount of circuitry. This can be achieved by utilizing the configuration bits that are used by the PTM block/OR gate configuration bits blocks.